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MRF49XA
3.15 Low Duty Cycle Mode
In Low Duty Cycle mode, the receiver periodically
wakes up for a short period and checks for the valid
FSK transmission in progress. The FSK transmission is
detected in the frequency range determined by
CFSREG and the baseband filter bandwidth is
determined by the RXCREG. The on time is
automatically extended until the DQI indicates a good
received signal condition.
The following facts need to be considered while
calculating the duty cycle on-time:
? The crystal oscillator, the synthesizer and the PLL
completely and all other interrupts are cleared. The
device then returns to the Low-Power Consumption
mode. Figure 3-13 depicts the Low-Power Duty Cycle
mode sequence.
The low duty cycle is calculated by using the DCMV
(DCSREG<7:1>) and WTMV (WTSREG<7:0>) bits, as
shown in Equation 3-3 . The time cycle is determined by
the WTSREG.
EQUATION 3-3:
DC = (DCMV<7:1> x 2 + 1)/WTMV<7:0> x 100%
need time to start (see Table 5-7 ).
? Depending on the DQTI, the device needs to
receive few valid data bits before the DQI signal
Note:
In Duty Cycle mode, the RXCEN bit must
be cleared and the WUTEN bit must be
set in PMCREG.
indicates a good signal condition (see
Register 2-8 ).
Selecting a short on-time can prevent the crystal
oscillator from starting, or the DQI signal will not go high
The registers associated with Low Duty Cycle mode
are:
? STSREG (see Register 2-1 )
even when the received signal has a good quality. The
MRF49XA is normally configured to work in FIFO mode.
However, when the device periodically wakes up from
Sleep mode, it switches to the Receive mode. If valid
FSK data is received, the device sends an interrupt to
the microcontroller and continues filling the RXFIFO. On
completion of transmission, the FIFO is read out
?
?
?
?
?
GENCREG (see Register 2-2 )
RCXREG (see Register 2-7 )
BBFCREG (see Register 2-8 )
PMCREG (see Register 2-13 )
WTSREG (see Register 2-14 )
FIGURE 3-13:
LOW-POWER DUTY CYCLE MODE SEQUENCE
Start/Send
Start/Send
Transmitter
Packet A
Packet A
Packet A
Packet
B. B. B. B.
Receiver
T WAKE -up
Receiving
Packet A
Packet A
Packet
B.
DQI
IRO
Microcontroller
Operation
DS70590C-page 64
FIFO Read
Preliminary
FIFO Read
? 2009-2011 Microchip Technology Inc.
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